Every FPGA design has interconnections of some form, either between internal blocks or from FPGA-to-FPGA....

This is possibly one of the most widely discussed topics in programmable logic design, but also one of the least understood....

A common complaint I hear from users that their FPGA design works "most of the time" but that every so often it boots up in a strange state or just fails to start working....

It can be very useful to extract a list of clock enable nets from a design, especially if you intend applying multicycle constraints....

The previous post about bitstream timestamps shows a way to automatically insert a timestamp into a bitstream such that it can be read back via JTAG or internally ...