Why you should adopt AXI-4 for all your FPGA interfaces

Every FPGA design has interconnections of some form, either between internal blocks or from FPGA-to-FPGA and designers often end up inventing some kind of new “protocol” from one design to the next. For your next design, consider using the AXI-4 standard for all of those interconnections – there are many good reasons for doing this:

• It’s a well established standard used in many applications. The standard documents are freely available from the ARM website.
• You no longer need to provide descriptions and timing waveforms for your interfaces in the FPGA design documentation – just reference the ARM AMBA standards. This is a huge time saver.
• Your design team only needs to learn and use one kind of protocol. Everyone “knows” the protocol and that eliminates confusion and misunderstanding.
• There are different “flavours” of AXI-4, from the simple handshaking of AXI Streaming, to the more complex AXI memory-mapped, so you can always find one to meet your needs.
• Xilinx uses AXI for all its IPs and for the interconnections in Zynq, so your design will become compatible with Xilinx solutions.
• In the Vivado Design Suite, there are multiple IPs available for checking and verifying your AXI interconnects, both in simulation and in hardware:
• AXI Protocol Verifiers
• AXI Traffic Generators
• AXI Bus Functional Model
• JTAG to AXI Master
• Having AXI interfaces on your custom logic allows it to be easily imported into the Vivado IP Integrator tool and rapidly connected to other AXI-based logic.