Using Tcl to find clock enable nets

It can be very useful to extract a list of clock enable nets from a design, especially if you intend applying multicycle constraints.

The Tcl procedure presented here reads a synthesized or implemented design and will list all nets that are connected to enable pins of synchronous primitives (flip-flops, BlockRAMS, etc).

Once the script has been run, a new Tcl command will be available to the user: report_clock_enables. This command can be run directly from the Vivado Tcl console and has several optional arguments:

  • -loads: For each clock enable net found, a list of their load cells will be included in the report.
  • -file filename: An output text file can be specified.
  • -w: If an output text file is specified that already exists, the -w options will allow it to be overwritten.

The tcl script can be downloaded here.