A generic VHDL ROM with content initialisation from a file

This post describes how to code a technology-independent VHDL ROM memory and the use of an external file for setting the initial contents.

  1. library ieee ;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_Std.all;
  4. library std ;
  5. use std.textio.all;
  8. entity spROM is
  9.  generic (initFile : string := "dummy_file_name.mif");
  10.  port (
  11.   CLK : in std_logic;
  12.   ADDRESS : in std_logic_vector;
  13.   DATAOUT : out std_logic_vector
  14. );
  15. end entity spROM;
  18. architecture arcspROM of spROM is
  20.  type romType is array(0 to 2**ADDRESS'length-1) of std_logic_vector(DATAOUT'length-1 downto 0);
  22.  -- uses VHDL 2008 hread
  23.  impure function initRomFromFile return romType is
  24.   file data_file : text open read_mode is initFile;
  25.   variable data_fileLine : line;
  26.   variable ROM : romType;
  27.  begin
  28.   for I in romType'range loop
  29.    readline(data_file, data_fileLine);
  30.    hread(data_fileLine, ROM(I));
  31.   end loop;
  32.   return ROM;
  33.  end function;
  35.  signal rom : romType := initRomFromFile;
  37.  attribute rom_style : string;
  38.  attribute rom_style of rom : signal is "block";
  41. begin
  43.  process (CLK)
  44.  begin
  45.   if (CLK'event and CLK = '1') then
  46.    DATAOUT <= rom(to_integer(unsigned(ADDRESS)));
  47.   end if;
  48.  end process;
  51. end architecture arcspROM;

Listing 2

A VHDL impure function is used so that it can reference the file name that is provided as a generic. Note also how the number of elements in the std_logic_vectors for ADDRESS and DATAOUT are not specified - they will be "inherited" from the top level file that instantiates the ROM.


The spROM module can then be instantiated in a higher-level VHDL file like this:

  1. library ieee ;
  2. use ieee.std_logic_1164.all;
  5. entity top_mem is
  6.  port (
  7.   CLK : in std_logic;
  8.   ADDRESS : in std_logic_vector(3 downto 0);
  9.   DATAOUT : out std_logic_vector(15 downto 0)
  10.  );
  11. end entity top_mem;
  13. architecture arc_top_mem of top_mem is
  15.  component spROM is
  16.   generic (initFile : string := "dummy_file_name.mif");
  17.   port (
  18.    CLK : in std_logic;
  19.    ADDRESS : in std_logic_vector;
  20.    DATAOUT : out std_logic_vector );
  21.  end component spROM_16;
  23. begin
  25.  U0 : spROM
  26.   generic map (initFile => "my_init_file.mif")
  27.   port map (
  28.    CLK => CLK,
  29.    ADDRESS => ADDRESS,
  30.    DATAOUT => DATAOUT );
  33. end architecture arc_top_mem;

Listing 3

A zip archive that includes the VHDL source files and an example memory initialisation file is available here.