AES-128 CTR mode Encryption/Decryption system for Vivado HLS

This design is a complete AES-128 CTR mode IP core written in C++ for synthesis with the Vivado HLS tools. The design contains both the encryptor/decryptor and the key scheduler modules. The input and output interfaces are AXI streaming.

One of the advantages of a C/C++ based approach to hardware is that the design can be optimized to produce different clock frequency, throughput and latency without modifying the actual code. The documentation included in the download available from my git hub examples of how to obtain throughputs of 1.25G, 2.5G and 10G just by modifying compiler directives (also known as “pragmas”).

AES-128 encryption/decryption system

If you have any questions or comments about this design, please email me at